A packet processing device usually needs to buffer the packets into a packet memory while it processes them. The size of some packets (for example Ethernet packets) is not known upfront, so the device needs to start storing the packet into the packet memory without knowing how large the packet is. Moreover, packets arrive at the device in an interleaved fashion, so the device is simultaneously storing several incoming packets into the packet memory.
One solution is to reserve as much packet memory as the maximum possible packet size, so once the start of a packet is detected, the packet starts to be stored at the current memory pointer; then the current memory pointer is updated by adding the maximum packet size, and becomes the memory pointer where the next incoming packet will be stored at. Once the packets are processed and transmitted, their space in the packet memory (the fixed maximum packet size) can be freed and reused for other packets. In this scheme, the management of the packet memory by the packet memory manager is simple and each packet is associated with a single pointer into the packet memory (where the packet starts).
The problem with this solution is that it wastes a lot of packet memory since a maximum packet size is allocated for each packet regardless of the size of the packet. This implies that the packet memory needs to be very large to accommodate all the packets that need to be simultaneously processed to meet the bandwidth demands of the device. Since the packet memory is a very expensive resource (especially if it is implemented on-chip using SRAM), this solution is not cost effective.
Accordingly, it would be desirable to provide improved techniques for packet memory management in high bandwidth packet processors.